{"text_format":"1","workbook":"xlsx","n_sheets":7,"sheets":["Title","Instructions","DDR3 Spec","DDR3 Config","System Config","Power Calcs","Summary"],"not_rendered":{"charts":2,"images":6,"macros":1,"external_links":0,"defined_names":7,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900"}

{"sheet":"Title","index":0,"n_rows":20,"n_cols":4,"rows_kept":20,"cut":false,"hidden":false,"merged":[]}
[]
[null,"File Name",":","DDR3_Power_Calc.XLSM"]
[null,"Revision",":",1.02]
[null,"Date",":","2020-11-02"]
[]
[null,"E-Mail",":","dramsupport@micron.com"]
[null,"Company",":","Micron Technology, Inc."]
[]
[null,"Description",":","Calculates the power consumed by a DDR3 and DDR3L SDRAM based on system use parameters and the device data sheet."]
[]
[null,"Limitations",":"]
[]
[null,"Notes",":"]
[]
[null,"Disclaimer",":","THIS SPREADSHEET IS FOR ESTIMATING PURPOSES ONLY. ANY INFORMATION PROVIDED HEREIN IS PROVIDED \"AS IS\" AND WITHOUT WARRANTIES OF ANY KIND.  MICRON WARRANTS ONLY THAT ITS PRODUCTS COMPLY WITH MICRON'S SPECIFICATION SHEET FOR THE PRODUCT AT THE TIME OF DELIVERY; PROVIDED THAT DEVIATIONS FROM SPECIFICATIONS WHICH DO NOT MATERIALLY AFFECT FORM, FIT OR FUNCTION OF SUCH PRODUCT IN THE SYSTEM AND CONFIGURATION IN OR FOR WHICH IT IS INITIALLY INSTALLED OR QUALIFIED BY CUSTOMER SHALL NOT BE DEEMED TO CONSTITUTE FAILURE TO COMPLY WITH SUCH SPECIFICATIONS."]
[null,null,null,"SEE MICRON'S STANDARD TERMS AND CONDITIONS OF SALE FOR COMPLETE WARRANTY DETAILS."]
[]
[]
[null,null,null,"Copyright © 2007 Micron Semiconductor Products, Inc."]
[null,null,null,"All rights reserved."]

{"sheet":"Instructions","index":1,"n_rows":41,"n_cols":6,"rows_kept":41,"cut":false,"hidden":false,"merged":[]}
[]
[]
[]
["Instructions for Use"]
[null,"DDR3 Spec tab (ALL MUST BE VERIFIED FOR A SPECIFIC DRAM DATA SHEET)"]
[null,null,"Inputs are required for all densities and speed grades that may be chosen."]
[null,null,"Enter VDD tolerance range in rows 6–7."]
[null,null,"Enter IDD values for the speed grade under investigation in rows 9–26. Note that there are entries for both x4/x8 devices, as well as x16. Also note the two separate entries for IDD3P, depending on the mode register setting."]
[null,null,"Timing restrictions in rows 28–36 are entered from the data sheet. These determine the test conditions for the IDD values and restrictions of normal device operation."]
[]
[null,"DDR3 Config  tab (ALL MUST BE ENTERED TO IDENTIFY DRAM TO BE USED FOR POWER CALCULATION)"]
[null,null,"Row 7 selects which DRAM density."]
[null,null,"Row 8 selects the number of DQs."]
[null,null,"Row 9 selects the starting speed grade."]
[null,null,"Row 10 selects low voltage or nominal. "]
[null,null,"Row 11 selects whether fast or slow exit is used for power-down exit."]
[]
[null,"DDR3 Spec tab (ALL MUST BE ENTERED FOR SPECIFIC SYSTEM)"]
[null,null,"Row 7 is the actual VDD the system is operating at. It is usually set to nominal conditions."]
[null,null,"Row 8 is the clock rate the DRAM is operating at. This is one half of the data rate."]
[null,null,"Row 9 is the burst length programmed in the mode register. (The model does not calculate power if burst interrupt is utilized.)"]
[null,null,"Row 10* is the amount of power that is drawn per output while driving read data from itself. ",null,null," "]
[null,null,"Row 11* is the amount of power that is drawn per output while terminating write data to itself. "]
[null,null,"Row 12* is the amount of power that is drawn per DQ while terminating read data at different DRAM (two or more loads). "]
[null,null,"Row 13* is the amount of power that is drawn per DQ while terminating write data at different DRAM (two or more loads). "]
[null,null,"     *These are system-dependent and must be calculated. The value may be approximated with a DC calculation (calculator                        provided) or more accurately determined using SPICE models."]
[null,null,"Row 15 is the time when all banks are in a precharged state. This is the amount of time when no bank has been activated."]
[null,null,"Row 16 is the percentage of time that all that banks are precharged when the device is in power-down state. This is the percentage of time when the DRAM is using IDD2P vs. IDD2F."]
[null,null,"Row 17 is the percentage of DRAM active time when CKE is LOW and the device is in the power-down state. This is the percentage of active time when the DRAM is using IDD3P current vs. IDD3N."]
[null,null,"Row 19 is the average time between ACT commands to the DRAM.  Under IDD0 or IDD1 conditions, this would be equal to tRC. If the DRAM is in interleaving bursts, it may be less than tRC. This value is now calculated off of page hit rate. Entering a number here will override the automatic calculation."]
[null,null,"Row 21 is the percentage of clocks that data is read from the DRAM. This would be equal to the average read bandwidth divided by peak read bandwidth."]
[null,null,"Row 22 is the percentage of clocks that data is written to the DRAM. This would be equal to the average read bandwidth divided by peak read bandwidth. "]
[null,null,"Row 23 is the page hit rate. 0% means there are no page hits (i.e., one read/write per each activate)."]
[null,null,"Row 24 is the percentage of clock cycles the DRAM under investigation is terminating read data from another device. It does not include time when a different DRAM on the bus may be terminating data."]
[null,null,"Row 25 is the percentage of clock cycles the DRAM under investigation is terminating write data from another device. It does not include time when a different DRAM on the bus may be terminating data."]
[]
[null,"Power Calcs tab"]
[null,null,"No inputs are required for this tab. It contains some of the detail calculations that provide information into the Summary tab. It can be used as a reference for further understanding the calculator, or you may jump straight to the Summary page for the final answer."]
[]
[null,"Summary tab"]
[null,null,"No inputs are required for this tab. It contains a summary of the power used by the DRAM. The power is broken out between:\n  — Power to read/write data to and from the DRAM\n  — Power to activate the rows\n  — Background power for standby modes and refresh"]

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[]
[]
[]
[null,null,null,"1Gb",null,null,null,null,null,null,null,null,null,null,"2Gb",null,null,null,null,null,null,null,null,null,null,"4Gb",null,null,null,null,null,null,null,null,null,null,"8Gb",null,null,null,null,null,null,null,null,null,null,"16Gb"]
["Parameter","Condition","Condition","-093E","-093","-107E","-107","-125E","-125","-15E","-187E","-187","-25",null,"-093E","-093","-107E","-107","-125E","-125","-15E","-187E","-187","-25",null,"-093E","-093","-107E","-107","-125E","-125","-15E","-187E","-187","-25",null,"-093E","-093","-107E","-107","-125E","-125","-15E","-187E","-187","-25",null,"-093E","-093","-107E","-107","-125E","-125","-15E","-187E","-187","-25"]
[null,"Maximum VDD",null,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,null,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,null,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,null,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,null,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,1.4350000000000001,null,"V"]
[null,"Minimum VDD",null,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,null,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,null,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,null,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,null,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,1.2829999999999999,null,"V"]
[]
["IDD0","Maximum active precharge current","x4/x8"," na",46," na",43," na",42,41,39," na"," na",null," na",46," na",43," na",42,41,39,"na"," na",null," na",31," na",29," na",28," na"," na"," na"," na",null," na"," na",69,69,67,67," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",55," na",51," na",49,48,46," na"," na",null," na",55," na",51," na",49,48,46," na"," na",null," na",34," na",32," na",32," na"," na"," na"," na",null," na"," na",69,69,67,67," na"," na"," na"," na",null," na"," na",85,85,83,83," na"," na"," na"," na",null,"mA"]
["IDD2P (Slow)","Maximum precharge power-down standby current(Slow Exit)","x4/x8"," na",12," na",12," na",12,12,12," na"," na",null," na",12," na",12," na",12,12,12," na"," na",null," na",12," na",11," na",10," na"," na"," na"," na",null," na"," na",11,11,11,11," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",12," na",12," na",12,12,12," na"," na",null," na",12," na",12," na",12,12,12," na"," na",null," na",12," na",12," na",12," na"," na"," na"," na",null," na"," na",11,11,11,11," na"," na"," na"," na",null," na"," na",22,22,22,22," na"," na"," na"," na",null,"mA"]
["IDD2P (Fast)","Maximum precharge power-down standby current(Fast Exit)","x4/x8"," na",15," na",15," na",15,15,15," na"," na",null," na",15," na",15," na",15,15,15," na"," na",null," na",13," na",11," na",11," na"," na"," na"," na",null," na"," na",16,16,14,14," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",15," na",15," na",15,15,15," na"," na",null," na",15," na",15," na",15,15,15," na"," na",null," na",14," na",12," na",12," na"," na"," na"," na",null," na"," na",16,16,14,14," na"," na"," na"," na",null," na"," na",27,27,25,25," na"," na"," na"," na",null,"mA"]
["IDD2N","Maximum precharge standby current","x4/x8"," na",23," na",23," na",23,23,23," na"," na",null," na",23," na",23," na",23,23,23," na"," na",null," na",22," na",17," na",16," na"," na"," na"," na",null," na"," na",38,38,36,36," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",23," na",23," na",23,23,23," na"," na",null," na",23," na",23," na",23,23,23," na"," na",null," na",22," na",17," na",17," na"," na"," na"," na",null," na"," na",38,38,36,36," na"," na"," na"," na",null," na"," na",49,49,47,47," na"," na"," na"," na",null,"mA"]
["IDD3P","Maximum active power-down standby current ","x4/x8"," na",17," na",17," na",17,17,17," na"," na",null," na",22," na",22," na",22,22,22," na"," na",null," na",17," na",15," na",15," na"," na"," na"," na",null," na"," na",38,38,36,36," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",17," na",17," na",17,17,17," na"," na",null," na",22," na",22," na",22,22,22," na"," na",null," na",19," na",17," na",17," na"," na"," na"," na",null," na"," na",38,38,36,36," na"," na"," na"," na",null," na"," na",49,49,47,47," na"," na"," na"," na",null,"mA"]
["IDD3N","Maximum active standby current","x4/x8"," na",40," na",37," na",35,33,31," na"," na",null," na",40," na",37," na",35,33,31," na"," na",null," na",23," na",21," na",20," na"," na"," na"," na",null," na"," na",53,53,51,51," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",43," na",38," na",37,36,33," na"," na",null," na",43," na",39," na",37,36,33," na"," na",null," na",25," na",23," na",22," na"," na"," na"," na",null," na"," na",53,53,51,51," na"," na"," na"," na",null," na"," na",64,64,62,62," na"," na"," na"," na",null,"mA"]
["IDD4R","Maximum read burst current","x4"," na",125," na",110," na",100,88,74," na"," na",null," na",120," na",106," na",96,84,70," na"," na",null," na",110," na",90," na",90," na"," na"," na"," na",null," na"," na",135,135,125,125," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x8"," na",125," na",110," na",100,88,74," na"," na",null," na",125," na",110," na",100,88,74," na"," na",null," na",110," na",90," na",90," na"," na"," na"," na",null," na"," na",135,135,125,125," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",180," na",155," na",135,115,95," na"," na",null," na",180," na",155," na",135,115,95," na"," na",null," na",130," na",120," na",110," na"," na"," na"," na",null," na"," na",195,195,185,185," na"," na"," na"," na",null," na"," na",211,211,201,201," na"," na"," na"," na",null,"mA"]
["IDD4W","Maximum write burst current","x4"," na",126," na",114," na",103,91,79," na"," na",null," na",122," na",110," na",99,87,75," na"," na",null," na",110," na",90," na",90," na"," na"," na"," na",null," na"," na",135,135,125,125," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x8"," na",126," na",114," na",103,91,79," na"," na",null," na",126," na",114," na",103,91,79," na"," na",null," na",110," na",90," na",90," na"," na"," na"," na",null," na"," na",135,135,125,125," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",184," na",164," na",146,127,107," na"," na",null," na",184," na",164," na",146,127,107," na"," na",null," na",140," na",130," na",120," na"," na"," na"," na",null," na"," na",195,195,185,185," na"," na"," na"," na",null," na"," na",211,211,201,201," na"," na"," na"," na",null,"mA"]
["IDD5B","Maximum burst refresh current","x4/x8"," na",170," na",165," na",160,160,155," na"," na",null," na",190," na",184," na",182,181,179," na"," na",null," na",160," na",152," na",152," na"," na"," na"," na",null," na"," na",250,250,245,245," na"," na"," na"," na",null," na"," na","na","na","na","na"," na"," na"," na"," na",null,"mA"]
[null,null,"x16"," na",170," na",165," na",160,160,155," na"," na",null," na",190," na",184," na",182,181,179," na"," na",null," na",160," na",156," na",156," na"," na"," na"," na",null," na"," na",250,250,245,245," na"," na"," na"," na",null," na"," na",261,261,256,256," na"," na"," na"," na",null,"mA"]
[]
[null,"tCK used for current measurements (see current notes)",null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,"ns"]
["tRRD","Minimum activate-to-activate timing (different bank)","x4/x8",6,6,6,6,6,6,6,7.5,7.5,10,null,6,6,6,6,6,6,6,7.5,7.5,10,null,6,6,6,6,6,6,6,7.5,7.5,10,null,6,6,6,6,6,6,6,7.5,7.5,10,null,6,6,6,6,6,6,6,7.5,7.5,10,null,"ns"]
[null,null,"x16",7.5,7.5,7.5,7.5,7.5,7.5,7.5,10,10,10,null,7.5,7.5,7.5,7.5,7.5,7.5,7.5,10,10,10,null,7.5,7.5,7.5,7.5,7.5,7.5,7.5,10,10,10,null,7.5,7.5,7.5,7.5,7.5,7.5,7.5,10,10,10,null,7.5,7.5,7.5,7.5,7.5,7.5,7.5,10,10,10,null,"ns"]
["tRC","Minimum activate-to-activate timing (same bank)",null,45.155000000000001,46.09,46.84,47.91,47.5,48.75,49.5,50.625,52.5,52.5,null,45.155000000000001,46.09,46.84,47.91,47.5,48.75,49.5,50.625,52.5,52.5,null,45.155000000000001,46.09,46.84,47.91,47.5,48.75,49.5,50.625,52.5,52.5,null,45.155000000000001,46.09,46.84,47.91,47.5,48.75,49.5,50.625,52.5,52.5,null,45.155000000000001,46.09,46.84,47.91,47.5,48.75,49.5,50.625,52.5,52.5,null,"ns"]
["tRAS","tRAS used for IDD0 calculation",null,36,36,34,34,35,35,36,37.5,37.5,37.5,null,36,36,34,34,35,35,36,37.5,37.5,37.5,null,36,36,34,34,35,35,36,37.5,37.5,37.5,null,36,36,34,34,35,35,36,37.5,37.5,37.5,null,36,36,34,34,35,35,36,37.5,37.5,37.5,null,"ns"]
["tRFC (MIN)","Minimum refresh-to-refresh cycle time",null,110,110,110,110,110,110,110,110,110,110,null,160,160,160,160,160,160,160,160,160,160,null,260,260,260,260,260,260,260,260,260,260,null,350,350,350,350,350,350,350,350,350,350,null,350,350,350,350,350,350,350,350,350,350,null,"ns"]
["tREFI","Average periodic refresh cycle time",null,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,null,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,null,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,null,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,null,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,7.8,null,"µs"]
["tCK (MIN)","Minimum tCK cycle rate",null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,0.93799999999999994,0.93799999999999994,1.07,1.07,1.25,1.25,1.5,1.875,1.875,2.5,null,"ns"]
["tCK (MAX)","Maximum tCK cycle rate",null,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,null,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,null,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,null,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,null,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,3.3,null,"ns"]
[]
[]
["                                         Do Not Go Below This Box                                                            Do Not Go Below This Box                                                           Do Not Go Below This Box                                                           Do Not Go Below This Box                                                             Do Not Go Below This Box                                                           Do Not Go Below This Box                                                           Do Not Go Below This Box                                                           Do Not Go Below This Box                  "]
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[null,null,"tCK  (MIN)",{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!D37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!O37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!Z37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AK37,'DDR3 Spec'!AV37))))","v":0.93799999999999994},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!E37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!P37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AA37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AL37,'DDR3 Spec'!AW37))))","v":0.93799999999999994},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!F37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!Q37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AB37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AM37,'DDR3 Spec'!AX37))))","v":1.07},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!G37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!R37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AC37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AN37,'DDR3 Spec'!AY37))))","v":1.07},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!H37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!S37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AD37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AO37,'DDR3 Spec'!AZ37))))","v":1.25},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!I37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!T37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AE37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AP37,'DDR3 Spec'!BA37))))","v":1.25},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!J37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!U37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AF37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AQ37,'DDR3 Spec'!BB37))))","v":1.5},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!K37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!V37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AG37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AR37,'DDR3 Spec'!BC37))))","v":1.875},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!L37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!W37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AH37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AS37,'DDR3 Spec'!BD37))))","v":1.875},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!M37,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!X37,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AI37,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AT37,'DDR3 Spec'!BE37))))","v":2.5},null,null,null,null,null,null,null,null,null,{"$f":"HLOOKUP($W$43,$D$43:$M$77,34)","v":0.93799999999999994}]
[null,null,"tCK (MAX)",{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!D38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!O38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!Z38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AK38,'DDR3 Spec'!AV38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!E38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!P38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AA38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AL38,'DDR3 Spec'!AW38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!F38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!Q38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AB38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AM38,'DDR3 Spec'!AX38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!G38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!R38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AC38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AN38,'DDR3 Spec'!AY38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!H38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!S38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AD38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AO38,'DDR3 Spec'!AZ38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!I38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!T38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AE38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AP38,'DDR3 Spec'!BA38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!J38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!U38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AF38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AQ38,'DDR3 Spec'!BB38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!K38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!V38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AG38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AR38,'DDR3 Spec'!BC38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!L38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!W38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AH38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AS38,'DDR3 Spec'!BD38))))","v":3.3},{"$f":"IF('DDR3 Config'!$G$1=1,'DDR3 Spec'!M38,IF('DDR3 Config'!$G$1=2,'DDR3 Spec'!X38,IF('DDR3 Config'!$G$1=3,'DDR3 Spec'!AI38,IF('DDR3 Config'!$G$1=4,'DDR3 Spec'!AT38,'DDR3 Spec'!BE38))))","v":3.3},null,null,null,null,null,null,null,null,null,{"$f":"HLOOKUP($W$43,$D$43:$M$77,35)","v":3.3}]
[]
["Parameter","Condition"]
[null,"Maximum VCC",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K12=1,'DDR3 Config'!L8,'DDR3 Config'!L9)","v":1.575}]
[null,"Minimum VCC",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K12=1,'DDR3 Config'!M8,'DDR3 Config'!M9)","v":1.425}]
[]
["IDD0","Maximum Active Precharge Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W48,'DDR3 Spec'!W47)","v":55}]
["IDD2P","Maximum Precharge Power-Down Standby Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!I1=2,L87,L86)","v":15}]
["IDD2N","Maximum Precharge Standby Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W54,'DDR3 Spec'!W53)","v":23}]
[null,null,null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W50,'DDR3 Spec'!W49)","v":12}]
[null,null,null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W52,'DDR3 Spec'!W51)","v":15}]
["IDD3P","Maximum Active Power-Down Standby Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W56,'DDR3 Spec'!W55)","v":17}]
["IDD3N","Maximum Active Standby Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W58,'DDR3 Spec'!W57)","v":43}]
["IDD4R","Maximum Read Burst Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W61,          IF('DDR3 Config'!K1=2,             'DDR3 Spec'!W60,             'DDR3 Spec'!W59          )             )","v":180}]
["IDD4W","Maximum Write BurstCurrent",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W64,          IF('DDR3 Config'!K1=2,             'DDR3 Spec'!W63,             'DDR3 Spec'!W62          )             )","v":184}]
["IDD5A","Maximum Burst Refresh Current",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W66,'DDR3 Spec'!W65)","v":170}]
[]
[null,"tCK used for current measurements (see current notes)",null,null,null,null,null,null,null,null,null,{"$f":"W69","v":0.93799999999999994}]
["tRRD","Minimum activate-to-activate timing (different bank)",null,null,null,null,null,null,null,null,null,{"$f":"IF('DDR3 Config'!K1=3,'DDR3 Spec'!W71,'DDR3 Spec'!W70)","v":7.5}]
["tRC","Minimum activate-to-activate timing (Same bank)",null,null,null,null,null,null,null,null,null,{"$f":"W72","v":46.09}]
["tRAS","tRAS used for IDD0 Calcualtion",null,null,null,null,null,null,null,null,null,36]
["tRFC(min)","Minimum refresh to refresh cycle time",null,null,null,null,null,null,null,null,null,110]
["tREFI","Average periodic refresh cycle time",null,null,null,null,null,null,null,null,null,7.8]
["tCK(min)","Minimum tCK cycle rate",null,null,null,null,null,null,null,null,null,0.93799999999999994]
["tCK(max)","Maximum tCK cycle rate",null,null,null,null,null,null,null,null,null,3.3]
[]
[]
[]
["Initial numbers are for reference only and must be verified with existing DRAM data sheets for accuracy prior to using the spreadsheet."]

{"sheet":"DDR3 Config","index":3,"n_rows":37,"n_cols":13,"rows_kept":37,"cut":false,"hidden":false,"merged":[[4,0,4,3]]}
[null,null,null,null,null,null,1,2,2,null,3]
[null,null,null,null,null,null,null,"Speed Grade","PD Exit Mode",null,"DQs per DRAM"]
[null,null,null,null,null,null,"1Gb",{"$f":"'DDR3 Spec'!D5","v":"-093E"},"0:Slow",1,"x4",4]
[null,null,null,null,null,null,"2Gb",{"$f":"'DDR3 Spec'!E5","v":"-093"},"1:Fast",1,"x8",8]
[{"$f":"_xlfn.CONCAT(IF(K12=1,\"DDR3\",\"DDR3L\"),\" SDRAM Configuration\")","v":"DDR3 SDRAM Configuration"},null,null,null,null,null,"4Gb",{"$f":"'DDR3 Spec'!F5","v":"-107E"},null,2,"x16",16]
[null,null,null,null,null,null,"8Gb",{"$f":"'DDR3 Spec'!G5","v":"-107"}]
[null,"DRAM Density",{"$f":"INDEX(G3:G7,G1)","v":"1Gb"},null,null,null,"16Gb",{"$f":"'DDR3 Spec'!H5","v":"-125E"},null,null,null,"Max VCC","Min VCC"]
[null,"Number of DQs per DRAM",{"$f":"INDEX(L3:L5,K1)","v":16},null,null,null,null,{"$f":"'DDR3 Spec'!I5","v":"-125"},null,null,"DDR3",1.575,1.425]
[null,"Speed Grade",{"$f":"INDEX(H3:H12,H1)","v":"-093"},null,null,null,null,{"$f":"'DDR3 Spec'!J5","v":"-15E"},null,null,"DDR3L",1.4350000000000001,1.2829999999999999]
[null,"DDR3 or DDR3L",null,null,null,null,null,{"$f":"'DDR3 Spec'!K5","v":"-187E"}]
[null,"Mode Register bit 12: Precharge PD Exit Mode",null,null,null,null,null,{"$f":"'DDR3 Spec'!L5","v":"-187"}]
[null,null,null,null,null,null,null,{"$f":"'DDR3 Spec'!M5","v":"-25"},null,null,1]
[null,null,null,null,null,null,null," "]
["Parameter","Condition","Value","Units",null,null,null," "]
[null,"Maximum VCC",{"$f":"IF(K12=1,L8,L9)","v":1.575},"V"]
[null,"Minimum VCC",{"$f":"IF(K12=1,M8,M9)","v":1.425},"V"]
[]
[null,"Number of DQ strobes (DQS) per DRAM",{"$f":"INDEX(J3:J5,K1)*2","v":4}]
[null,"Number of data mask (DM) per DRAM",{"$f":"INDEX(J3:J5,K1)","v":2},null,null,null,null,null,null," "]
[]
["IDD0","Maximum active precharge current",{"$f":"'DDR3 Spec'!L83","v":55},"mA"]
["IDD2P","Maximum precharge power-down standby current",{"$f":"'DDR3 Spec'!L84","v":15},"mA"]
["IDD2N","Maximum precharge standby current",{"$f":"'DDR3 Spec'!L85","v":23},"mA"]
["IDD3P","Maximum active power-down standby current",{"$f":"'DDR3 Spec'!L88","v":17},"mA"]
["IDD3N","Maximum active standby current",{"$f":"'DDR3 Spec'!L89","v":43},"mA"]
["IDD4R","Maximum read burst current",{"$f":"'DDR3 Spec'!L90","v":180},"mA"]
["IDD4W","Maximum write burst current",{"$f":"'DDR3 Spec'!L91","v":184},"mA"]
["IDD5A","Maximum burst refresh current",{"$f":"'DDR3 Spec'!L92","v":170},"mA"]
[]
[null,"tCK used for current measurements (see current notes)",{"$f":"'DDR3 Spec'!L94","v":0.93799999999999994},"ns"]
["tRRD","Minimum activate-to-activate timing (different bank)",{"$f":"'DDR3 Spec'!L95","v":7.5},"ns"]
["tRC","Minimum activate-to-activate timing (same bank)",{"$f":"'DDR3 Spec'!L96","v":46.09},"ns"]
["tRAS","tRAS used for IDD0 calculation",{"$f":"'DDR3 Spec'!L97","v":36},"ns"]
["tRFC (MIN)","Minimum refresh-to-refresh cycle time",{"$f":"'DDR3 Spec'!L98","v":110},"ns"]
["tREFI","Average periodic refresh cycle time",{"$f":"'DDR3 Spec'!L99","v":7.8},"µs"]
["tCK (MIN)","Minimum tCK cycle rate",{"$f":"'DDR3 Spec'!L100","v":0.93799999999999994},"ns"]
["tCK (MAX)","Maximum tCK cycle rate",{"$f":"'DDR3 Spec'!L101","v":3.3},"ns"]

{"sheet":"System Config","index":4,"n_rows":40,"n_cols":31,"rows_kept":40,"cut":false,"hidden":false,"merged":[[35,1,35,2],[34,1,34,2],[3,6,3,13],[3,14,3,21],[10,4,11,4],[12,4,13,4]]}
[]
[]
[]
[null,null,null,null,null,null,"READ  I/O  Power",null,null,null,null,null,null,null,"WRITE  I/O  Power"]
[null,"DRAM Usage Conditions in the System Environment"]
[]
[null,"System VDD",1.5,"V",{"$f":"IF(C7<'DDR3 Config'!C16,\"ERROR, VCC too Low\",IF(C7>'DDR3 Config'!C15,\"ERROR, too High\",\"\"))","v":""}]
[null,"System CK frequency",800,"MHz",{"$f":"IF(C8+1<1000/'DDR3 Config'!C37,\"ERROR, lower of operaitonal frequency range\",IF(C8 > 1000 /'DDR3 Config'!C36,\"ERROR, higher of operaitonal frequency range\",\"\"))","v":""}]
[null,"Burst length",8,null,"must be either 4 or 8 "]
[]
["PdqRD","DDR3 SDRAM output power per individual DQ on this DRAM during READs from this DRAM",{"$f":"IF(K18= \"na\",0, K18) +IF(K19= \"na\",0, K19)","v":5.4514886305672654},"mW","This value is the DRAM I/O power plus module series resistor power per DQ.   The calculator to the right will estimate and populate the entries to the left"]
["PdqWR","DDR3 SDRAM termination power per individual DQ during WRITEs to this DRAM",{"$f":"IF(S18= \"na\",0, S18) +IF(S19= \"na\",0, S19)","v":20.623755928036896},"mW",null,null,null,"Enter values in dark green boxes below",null,null,null,null,null,null,null,"Enter values in dark green boxes below"]
["PdqRDoth","DDR3 SDRAM termination power per individual DQ during READs from other DRAM",{"$f":"IF(M18= \"na\",0, M18) +IF(M19= \"na\",0, M19)","v":29.678594669847321},"mW","This value is the termination power plus module series resistor power per DQ.   The calculator to the right will estimate and populate the entries to the left",null,null,"RTTuC=",120,"Rz1=",34,"RTTu2=",40,null,null,"RzC=",34,"RTTu1=",60,"RTTu2=",{"$f":"M13","v":40},null,null,"IRZC",{"$f":"1*Q17/Q13","v":14.635180995475114},null,"IRTTpu1",{"$f":"1000*((Q15-0.001*S17)/S13)","v":16.211821266968329},null,"IRTTpu1",{"$f":"1000*((Q15-0.001*U17)/U13)","v":22.35576923076923}]
["PdqWRoth","DDR3 SDRAM termination power per individual DQ during WRITEs to other DRAM",{"$f":"IF(U18= \"na\",0, U18) +IF(U19= \"na\",0, U19)","v":29.945220044378697},"mW",null,null,null,"RTTdC=",120,"Rs1=",15,"RTTd2=",40,null,null," ",null,"RTTd1=",60,"RTTd2=",{"$f":"M14","v":40},null,null,null,null,null,"IRTTpd1",{"$f":"1*S17/S14","v":8.7881787330316747},null,"IRTTpd1",{"$f":"1*U17/U14","v":15.144230769230768}]
[null,null,null,null,null,null,null,"VDDq=",{"$f":"$C$7","v":1.5},null,null,"Rs2=",15,null,null,"VDDq=",{"$f":"$C$7","v":1.5},"Rs1=",4,"Rs2=",{"$f":"M15","v":15},null,null,null,null,null,"IRS1",{"$f":"1*(S17-Q17)/S15","v":7.4236425339366434},null,"IRS1",{"$f":"1*(U17-Q17)/U15","v":7.2115384615384563}]
["BNK_PRE%","The percentage of time that all banks on the DRAM are in a precharged state",0.25,null,null,null,null,"Calculated values in light green boxes below",null,null,null,null,null,null,null,"Calculated values in light green boxes below"]
["CKE_LO_PRE%","The percentage of the all bank precharge time for which CKE is held LOW",0.25,null,null,null,null,"N3=      (mV)  ",{"$f":"IF(I15>0,1000*((I15/2)*(K13+K14)/((K13+K14)+IF(M13>0,IF(M14>0,(((I13*I14)/(I13+I14))*((M13*M14)/(M13+M14)+M15)/((I13*I14)/(I13+I14)+((M13*M14)/(M13+M14)+M15))),(I13*I14)/(I13+I14)),(I13*I14)/(I13+I14)))),\"na\")","v":516.83937823834196},"N1=      (mV)  ",{"$f":"IF(K13>0,         1000* (       I17*0.001  *K13/(K13+K14)),\"na\")","v":358.62324204293117},"N2=      (mV)  ",{"$f":"   IF(M13>0,       IF(M14>0,      1000*         ( I17*0.001+ 1*M15* ( I17*0.001/(K13+K14)  - 0.004)),   \"na\"),   \"na\")","v":615.05551443375282},null,null,"N3=      (mV)  ",{"$f":"IF(Q15>0,   1000*( (Q15/2 ) *   Q13    / (    IF(U13>0, IF(U14>0,    ( ( ((S13*S14)/(S13+S14)+S15 ) *  ((U13*U14)/(U13+U14)+U15)) / ( ((S13*S14)/(S13+S14)+S15)  +  ((U13*U14)/(U13+U14)+U15))), ((S13*S14)/(S13+S14)+S15 ) ), ((S13*S14)/(S13+S14)+S15 ) )        +Q13)      ),\"na\")","v":497.59615384615387},"N1=      (mV)  ",{"$f":"IF(S13>0,IF(S14>0,    Q17+    (1000*Q15/2-Q17)     *     S15 /  ((S13*S14)/(S13+S14) + S15 ),\"na\"),\"na\")","v":527.29072398190044},"N2=      (mV)  ",{"$f":"IF(U13>0,IF(U14>0,    Q17+    (1000*Q15/2-Q17)     *     U15 /  ((U13*U14)/(U13+U14) + U15 ),\"na\"),\"na\")","v":605.76923076923072}]
["CKE_LO_ACT%","The percentage of the at least one bank active time for which CKE is held LOW",0.25,null,{"$f":"IF(1-C18<C22+C23,\"ERROR, CKE HI must be greater than READ and WRITE output cycles\",\"\")","v":""},null,null,"RTTC =   (mW)",{"$f":"IF(I13>0,IF(I14>0,  1000*   (((I15-I17*0.001)/I13)*((I15-I17*0.001)/I13)*I13)  +  1000*   (((I17*0.001)/I14)*((I17*0.001)/I14)*I14),\"na\"),\"na\")","v":10.281064592338053},"Rz =   (mW)",{"$f":"    IF(K13>0,         1000*  (I17*0.001/(K13+K14)) * (I17*0.001/(K13+K14))   *K13, \"na\")","v":3.7826655803936129},"RTTd2 =   (mW)",{"$f":"IF(M13>0,IF(M14>0,(1000*(((I15-0.001*M17)/M13)*((I15-0.001*M17)/M13)*M13   +  (0.001*M17/M14)*(0.001*M17/M14)*M14) ),\"na\"),\"na\")","v":29.035500709236956},null,null,"Rz =   (mW)",{"$f":"    IF(Q13>0,         0.001*  (Q17/(Q13)) * (Q17/(Q13))    *Q13, \"na\")","v":7.282409774190743},"RTTd1 =   (mW)",{"$f":"IF(S13>0,IF(S14>0,   1000*( (1*          ((Q15-0.001*S17)/S13)  * ((Q15-0.001*S17)/S13) *S13     +     (0.001*S17/S14) * (0.001*S17/S14) *S13   )),\"na\"),\"na\")","v":20.403314054150204},"RTTd2 =   (mW)",{"$f":"IF(U13>0,IF(U14>0,    1000*(1*          ((Q15-0.001*U17)/U13)  * ((Q15-0.001*U17)/U13) *U13     +     (0.001*U17/U14) * (0.001*U17/U14) *U13   ),\"na\"),\"na\")","v":29.165125739644971}]
[null,null,null,null,null,null,null,null,null,"Rs1 =   (mW)",{"$f":"IF(K13>0,IF(K14>0,1000*(I17*0.001/(K13+K14))*(I17*0.001/(K13+K14))*K14,\"na\"),\"na\")","v":1.668823050173653},"Rs2=   (mW)",{"$f":"IF(M13>0,IF(M14>0,     IF(M15>0,         1000*(   ( (0.001*M17-0.001*I17)/M15) * ( (0.001*M17-0.001*I17)/M15)* M15),\"na\"),\"na\"),\"na\")","v":0.64309396061036561},null,null,null,null,"Rs1=   (mW)",{"$f":"IF(S13>0,IF(S14>0,     IF(S15>0,0.001*((       ((S17-Q17)/S15) * ((S17-Q17)/S15)   *  S15               )   ),0),\"na\"),\"na\")","v":0.22044187388669306},"Rs2=   (mW)",{"$f":"IF(U13>0,IF(U14>0,     IF(U15>0,   0.001*(       ((U17-Q17)/U15) * ((U17-Q17)/U15)   *  U15                  ),0),\"na\"),\"na\")","v":0.78009430473372676}]
["PH%","Page hit rate",0.5,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,1.5]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,1.35]
["RDsch%","The percentage of clock cycles which are outputting read data from the DRAM",0.3,null,{"$f":"IF(SUM(C22+C23+C25+C26)*8/C9>1,\"Data Bus utilization is too high\",\"\")","v":""},null,null,null,null,null,null,null," "]
["WRsch%","The percentage of clock cycles which are inputting write data to the DRAM",0.3]
[null,null,{"$f":"C22/(C23+C22)","v":0.5},null,"ratio of reads to writes"]
["termRDsch%","The percentage of clock cycles which are terminating read data to another DRAM",0,null,"must be 0% for a 1-rank system"]
["termWRsch%","The percentage of clock cycles which are terminating write data to another DRAM",0,null,"must be 0% for a 1-rank system"]
[]
["tRRDsch","The average time between ACT commands to this DRAM (includes ACT to same or different banks in the same DRAM device)",{"$f":"INT(C40*10000/C8)/10","v":16.600000000000001},"ns",""," ",null,null,null,null,null,null,null,null," "]
[null,null,null,null,"The above is calculated from page hit rate read/write bus utilization. No entry is necessary."]
[]
[]
[]
[]
[]
[null,"Values that may be updated are shown in green. This will be dependent on how the system accesses the DRAM.",null,null,null,null,null,null," "]
[null,"Calculated values in light green.",null,null,null,null,null,null," "]
[]
[]
[null,"Average clocks between column",{"$f":"C9/2/(C23+C22)","v":6.666666666666667}]
[null,"Average Clocks between Rows",{"$f":"C39/(1-C20)","v":13.333333333333334}]

{"sheet":"Power Calcs","index":5,"n_rows":35,"n_cols":12,"rows_kept":35,"cut":false,"hidden":false,"merged":[[26,6,26,7],[26,10,26,11]]}
[]
[]
[]
[]
[{"$f":"CONCATENATE(\"System Derating for \",C33,\" \",IF('DDR3 Config'!K12=1,\"DDR3\",\"DDR3L\"),\" SDRAM (x\",C34,\", \",C35,\" Speed Grade)\")","v":"System Derating for 1Gb DDR3 SDRAM (x16, -093 Speed Grade)"}]
[]
["Power is calculated based upon data sheet test conditions and maximum limits, scaled for used conditions an actual VDD.  and finally scaled for the frequency being used. All parameters are calculated and require no user input."]
[]
[]
[null,"Power Based on Data Sheet Test Conditions and Maximum Limits",null,null,null,"Power Derated for System Usage Conditions Input into This Model",null,null,null,"Power Scaled for Actual System Conditions (DRAM Usage, CK Frequency, and VCC)"]
["Background power used during precharge power-down","Pds(PRE_PDN)",{"$f":"+'DDR3 Config'!C22*'DDR3 Config'!C$15","v":23.625},"mW",null,"Psch(PRE_PDN)",{"$f":"C11*'System Config'!C16*'System Config'!C17","v":1.4765625},"mW",null,"Psys(PRE_PDN)",{"$f":"+G11*('System Config'!C$7/'DDR3 Config'!C$15)^2*IF('DDR3 Config'!I1=2,'System Config'!C$8/1000*'DDR3 Config'!C$30,1)","v":1.0050000000000001},"mW"]
["Background power used during idle standby","Pds(PRE_STBY)",{"$f":"+'DDR3 Config'!C23*'DDR3 Config'!C$15","v":36.225000000000001},"mW",null,"Psch(PRE_STBY)",{"$f":"C12*'System Config'!C16*(1-'System Config'!C17)","v":6.7921875000000007},"mW",null,"Psys(PRE_STBY)",{"$f":"+G12*('System Config'!C$7/'DDR3 Config'!C$15)^2*'System Config'!C$8/1000*'DDR3 Config'!C$30","v":4.623000000000002},"mW"]
["Background power used during active power-down","Pds(ACT_PDN)",{"$f":"+'DDR3 Config'!C24*'DDR3 Config'!C$15","v":26.774999999999999},"mW",null,"Psch(ACT_PDN)",{"$f":"C13*(1-'System Config'!C16)*'System Config'!C18","v":5.0203124999999993},"mW",null,"Psys(ACT_PDN)",{"$f":"+G13*('System Config'!C$7/'DDR3 Config'!C$15)^2*'System Config'!C$8/1000*'DDR3 Config'!C$30","v":3.4170000000000003},"mW"]
["Background power used during active standby","Pds(ACT_STBY)",{"$f":"+'DDR3 Config'!C25*'DDR3 Config'!C$15","v":67.724999999999994},"mW",null,"Psch(ACT_STBY)",{"$f":"C14*(1-'System Config'!C16)*(1-'System Config'!C18)","v":38.095312499999999},"mW",null,"Psys(ACT_STBY)",{"$f":"+G14*('System Config'!C$7/'DDR3 Config'!C$15)^2*'System Config'!C$8/1000*'DDR3 Config'!C$30","v":25.929000000000002},"mW"]
["Background power to complete refreshes","Pds(REF)",{"$f":"('DDR3 Config'!C28-'DDR3 Config'!C25)*'DDR3 Config'!C34/'DDR3 Config'!C35/1000*'DDR3 Config'!C15","v":2.8208653846153848},"mW",null,"Psch(REF)",{"$f":"C15","v":2.8208653846153848},"mW",null,"Psys(REF)",{"$f":"+G15*('System Config'!C$7/'DDR3 Config'!C$15)^2","v":2.5586080586080593},"mW"]
["DRAM power for ACT/PRE commands","Pds(ACT)",{"$f":"+('DDR3 Config'!C21-('DDR3 Config'!C25*'DDR3 Config'!C33/'DDR3 Config'!C32+'DDR3 Config'!C23*('DDR3 Config'!C32-'DDR3 Config'!C33)/'DDR3 Config'!C32))*'DDR3 Config'!C$15","v":25.795964417444125},"mW",null,"Psch(ACT)",{"$f":"+C16*'DDR3 Config'!C32/'System Config'!C28","v":71.622650602409621},"mW",null,"Psys(ACT)",{"$f":"+G16*('System Config'!C$7/'DDR3 Config'!C$15)^2","v":64.963855421686745},"mW"]
["DRAM write power","Pds(WR)",{"$f":"+('DDR3 Config'!C27-'DDR3 Config'!C$25)*'DDR3 Config'!C$15*8/'System Config'!C9","v":222.07499999999999},"mW",null,"Psch(WR)",{"$f":"+C17*'System Config'!C23","v":66.622499999999988},"mW",null,"Psys(WR)",{"$f":"+G17*('System Config'!C$7/'DDR3 Config'!C$15)^2*'System Config'!C$8/1000*'DDR3 Config'!C$30","v":45.345599999999997},"mW"]
["DRAM read power","Pds(RD)",{"$f":"+('DDR3 Config'!C26-'DDR3 Config'!C$25)*'DDR3 Config'!C$15*8/'System Config'!C9","v":215.77500000000001},"mW",null,"Psch(RD)",{"$f":"+C18*'System Config'!C22","v":64.732500000000002},"mW",null,"Psys(RD)",{"$f":"+G18*('System Config'!C$7/'DDR3 Config'!C$15)^2*'System Config'!C$8/1000*'DDR3 Config'!C$30","v":44.059200000000004},"mW"]
["DQ output power","Pds(DQ)",{"$f":"+('System Config'!C11*('DDR3 Config'!C$8+'DDR3 Config'!C18))","v":109.02977261134531},"mW",null,"Psch(DQ)",{"$f":"+C19*'System Config'!C22","v":32.708931783403592},"mW",null,"Psys(DQ)",{"$f":"+G19","v":32.708931783403592},"mW"]
["Term power for writes","Pds(termW)",{"$f":"+('System Config'!C12*('DDR3 Config'!C$8+'DDR3 Config'!C$18+'DDR3 Config'!C$19))","v":453.72263041681174},"mW",null,"Psch(termW)",{"$f":"+C20*'System Config'!C23","v":136.11678912504351},"mW",null,"Psys(termW)",{"$f":"+G20","v":136.11678912504351},"mW"]
["Term power for reads from another rank","Pds(termRoth)",{"$f":"+('System Config'!C13*('DDR3 Config'!C$8+'DDR3 Config'!C$18))","v":593.57189339694639},"mW",null,"Psch(termRoth)",{"$f":"+C21*'System Config'!C25","v":0},"mW",null,"Psys(termRoth)",{"$f":"+G21","v":0},"mW"]
["Term power for writes from another rank","Pds(termWoth)",{"$f":"+('System Config'!C14*('DDR3 Config'!C$8+'DDR3 Config'!C$18+'DDR3 Config'!C$19))","v":658.79484097633133},"mW",null,"Psch(termWoth)",{"$f":"+C22*'System Config'!C26","v":0},"mW",null,"Psys(termWoth)",{"$f":"+G22","v":0},"mW"]
[]
[null,null,null,null,null,null,null,null,null,"Total DRAM Power Consumed",{"$f":"SUM(K11:K20)","v":360.72698438874193},"mW"]
[null,null,null,null,null,null,null,null,null,"2nd rank DRAM Power Consumed",{"$f":"SUM(K21:K22)","v":0},"mW"]
[]
[]
[]
["VCC",null,{"$f":"'System Config'!C7","v":1.5}]
["FREQ",null,{"$f":"'System Config'!C8","v":800}]
[]
["Device"]
["Density",null,{"$f":"'DDR3 Config'!C7","v":"1Gb"}]
["IO",null,{"$f":"'DDR3 Config'!C8","v":16}]
["Speed Grade",null,{"$f":"'DDR3 Config'!C9","v":"-093"}]

{"sheet":"Summary","index":6,"n_rows":55,"n_cols":17,"rows_kept":55,"cut":false,"hidden":false,"merged":[[7,1,7,4]]}
[]
[]
[]
[]
[{"$f":"CONCATENATE('DDR3 Config'!C7,\" \",IF('DDR3 Config'!K12=1,\"DDR3\",\"DDR3L\"),\" SDRAM with \",'DDR3 Config'!C8,\" DQs and a \",'DDR3 Config'!C9,\" Speed Grade\")","v":"1Gb DDR3 SDRAM with 16 DQs and a -093 Speed Grade"}]
[]
[null,null,{"$f":"CONCATENATE(A49,\" \",A50,\" \",A51,\" All parameters are calculated and require no user input.\")","v":"System is operating at 800 MHz clock with VDD = 1.5V. Read bandwidth is 960 MT/s with write bandwidth of 960 MT/s. The DRAM terminates  0 MT/s. ACT commands are separated by 16.6ns on average. All parameters are calculated and require no user input."}]
[null,"Psys Power Consumption Summary"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null," "," "]
[null,"ACT",null,{"$f":"'Power Calcs'!K16","v":64.963855421686745},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$10","v":"ACT"},{"$f":"$D$10","v":64.963855421686745}]
[null,null,"Total Activate Power",{"$f":"D10","v":64.963855421686745},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$12","v":"RD"},{"$f":"$D$12","v":44.059200000000004}]
[null,"RD",null,{"$f":"'Power Calcs'!K18","v":44.059200000000004},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$13","v":"WR"},{"$f":"$D$13","v":45.345599999999997}]
[null,"WR",null,{"$f":"'Power Calcs'!K17","v":45.345599999999997},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$14","v":"READ I/O"},{"$f":"$D$14","v":32.708931783403592}]
[null,"READ I/O",null,{"$f":"'Power Calcs'!K19","v":32.708931783403592},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$15","v":"Write ODT"},{"$f":"$D$15","v":136.11678912504351}]
[null,"Write ODT",null,{"$f":"'Power Calcs'!K20","v":136.11678912504351},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$17","v":"ACT_STBY"},{"$f":"$D$17","v":25.929000000000002}]
[null,null,"Total RD/WR/Term Power",{"$f":"+D12+D13+D14+D15","v":258.23052090844709},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$18","v":"PRE_STBY"},{"$f":"$D$18","v":4.623000000000002}]
[null,"ACT_STBY",null,{"$f":"'Power Calcs'!K14","v":25.929000000000002},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$19","v":"ACT_PDN"},{"$f":"$D$19","v":3.4170000000000003}]
[null,"PRE_STBY",null,{"$f":"'Power Calcs'!K12","v":4.623000000000002},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$20","v":"PRE_PDN"},{"$f":"$D$20","v":1.0050000000000001}]
[null,"ACT_PDN",null,{"$f":"'Power Calcs'!K13","v":3.4170000000000003},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$21","v":"REF"},{"$f":"$D$21","v":2.5586080586080593}]
[null,"PRE_PDN",null,{"$f":"'Power Calcs'!K11","v":1.0050000000000001},"mW",null,null,null,null,null,null,null,null,null,null,{"$f":"$B$24","v":"TERM 2nd rank"},{"$f":"$D$24","v":0}]
[null,"REF",null,{"$f":"'Power Calcs'!K15","v":2.5586080586080593},"mW",null,null,null,null,null,null,null,null,null,null," "]
[null,null," Total Background  Power",{"$f":"SUM(D17:D21)","v":37.532608058608062},"mW",null,null,null,null,null,null,null,null,null,null," "]
[null,"Total DDR3 SDRAM Power",null,{"$f":"+D16+D11+D22","v":360.72698438874187},"mW",null,null,null,null,null,null,null,null,null,null," "]
[null,"TERM 2nd rank",null,{"$f":"+'Power Calcs'!K21+'Power Calcs'!K22","v":0},"mW",null,null,null,null,null,null,null,null,null,null," "]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null," "]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[{"$f":"CONCATENATE(\"System is operating at \",'System Config'!C8,\" MHz clock with VDD = \",'System Config'!C7,\"V.\")","v":"System is operating at 800 MHz clock with VDD = 1.5V."}]
[{"$f":"CONCATENATE(\"Read bandwidth is \",B52,\" MT/s with write bandwidth of \",B53,\" MT/s. The DRAM terminates  \",B54,\" MT/s.\")","v":"Read bandwidth is 960 MT/s with write bandwidth of 960 MT/s. The DRAM terminates  0 MT/s."}]
[{"$f":"CONCATENATE(\"ACT commands are separated by \",'System Config'!C28,\"ns on average.\")","v":"ACT commands are separated by 16.6ns on average."}]
[null,{"$f":"INT('System Config'!C8*'System Config'!C22*'DDR3 Config'!C8/8*20+0.999)/10","v":960},"MB/sec"]
["Read Bandwidth",{"$f":"INT('System Config'!C8*'System Config'!C23*'DDR3 Config'!C8/8*20+0.99)/10","v":960},"MB/sec"]
["Write Bandwidth",{"$f":"INT('System Config'!C8*('System Config'!C26+'System Config'!C25)*'DDR3 Config'!C8/8*20+0.99)/10","v":0},"MB/sec"]
["Term"]